1. Field of the Invention
The invention relates to an error correction code (ECC) decoder and, more particularly, to an ECC decoder capable of saving hardware cost.
2. Description of Related Art
FIG. 1 is a block diagram of a conventional decoder 100 capable of processing erasure and errata correction in parallel. As shown, the decoder 100 includes a syndrome calculation device 110, a syndrome modification device 120, a key equation solving device 130, a Chien search device 140 and an errata evaluation device 150.
The syndrome calculation device 110 receives a code word R(x) of a coded signal for a syndrome calculation to thereby output a syndrome polynomial S(x). FIG. 2 is a block diagram of the syndrome calculation device 110, which is essentially composed of module-2 adders 210, registers 220 and finite-field constant multipliers 230, where r0,r1, . . . ,rn−2,rn−1 indicate the code word R(x), and αi indicates an errata position. The syndrome modification device 120 modifies the syndrome polynomial S(x), and accordingly the key equation solving device 130 can effectively generate an erasure and errata locator polynomial σ(X) and an erasure and errata evaluator polynomial ω(x). FIG. 3 is a block diagram of the key equation solving device 130, which is essentially composed of module-2 adders 310, registers 320 and finite-field constant multipliers 330.
As shown in FIG. 1, the decoder 100 is typically divided into three pipelines in order to increase the decoding speed. Generally, the syndrome calculation performed by the syndrome calculator is not merged into a pipeline with other operations. The syndrome calculation requires successively reading data from memory and writing updated data back to the memory after the data is decoded, which increases the complexity of memory access control. In addition, the syndrome calculation and other pipelines may be performed concurrently, and accordingly a specific circuit is required in the syndrome calculation, which increases the die size and the hardware cost.
Therefore, it is desirable to provide an improved error correction code decoder to mitigate and/or obviate the aforementioned problems.